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Qwestrum Engineering360 · Computer & Hardware · Computer Architecture

Memory Hierarchy

Memory hierarchy balances speed, cost, and capacity using locality principles.

Exam tip: keep SI units consistent end-to-end, write the governing relation symbolically before substituting, and sanity-check magnitude and sign.

Key formulas & points

Skim these first — then read the full notes below.

Registers to cache to RAM to storage pyramid
Write-through vs write-back cache policy
Virtual memory extends apparent RAM via paging

Topic details

Introduction

Stallings and Hamacher explain hierarchy as the main reason modern CPUs remain efficient despite slow main memory. B.Tech numericals mostly use AMAT and miss-rate sensitivity.

Key relations & formulas

Formulas (Indian textbook notation)

$AMAT = hit_{time} + miss_{rate} \times miss_{penalty}$

Formulas (Indian textbook notation)

$locality: temporal (reuse) + spatial (adjacent)$

Formulas (Indian textbook notation)

$memory wall: CPU speed grows faster than DRAM latency$

Notation and sign conventions

Relation 1 —

AMAT = hit_{time} + miss_{rate} \times miss_{penalty}

Formulas (Indian textbook notation)

$AMAT = hit_{time} + miss_{rate} \times miss_{penalty}$

Write this relation with symbols exactly as in Computer System Architecture — Morris Mano before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

Relation 2 —

locality: temporal

Formulas (Indian textbook notation)

$locality: temporal (reuse) + spatial (adjacent)$

Write this relation with symbols exactly as in Computer System Architecture — Morris Mano before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

Relation 3 —

memory wall: CPU speed grows faster than DRAM latency

Formulas (Indian textbook notation)

$memory wall: CPU speed grows faster than DRAM latency$

Write this relation with symbols exactly as in Computer System Architecture — Morris Mano before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

Concept in depth

Upper levels are small and fast, lower levels are large and slow. Temporal locality justifies keeping recently used blocks, while spatial locality motivates block transfers. AMAT links design policy to measurable performance. Virtual memory isolates processes and extends usable address space at the cost of page faults when locality breaks down.

Assumptions and validity limits

State assumptions explicitly before using any relation for memory hierarchy — steady state, uniform properties, linear elastic material, ideal gas, incompressible flow, etc., as applicable.

Wrong assumptions invalidate the entire solution even when the formula is correct. In Computer Architecture viva and GATE descriptive questions, listing valid assumptions often earns separate marks.

Step-by-step problem approach

1. Read the question and list given data with SI units (common in Computer Architecture papers).
2. Draw a neat labelled diagram where applicable — examiners in Indian universities award diagram marks even when arithmetic slips.
3. Identify which relation from this topic applies to memory hierarchy.
4. Use equation 1:

AMAT = hit_{time} + miss_{rate} \times miss_{penalty}

.
5. Use equation 2:

locality: temporal

.
6. Substitute values, compute, and verify units and sign (direction).
7. State conclusion in one line — e.g. safe/unsafe, stable/unstable, feasible/infeasible.

Applications & exam relevance

Memory Hierarchy appears in processor and system design. In Indian computer hardware curricula this topic is tested because it connects theory to CPU, memory hierarchy, and I/O.

GATE and semester exams often combine memory hierarchy with earlier units — revise prerequisites before attempting mixed problems.

Industry interview panels sometimes ask: "Where did you use memory hierarchy?" — answer with a lab, mini-project, or plant visit example if possible.

Common mistakes in exams

Many answers add miss penalty directly to access time without multiplying by miss rate. Another error is mixing hit ratio and miss ratio in substitution.

Quick revision checklist

Before attempting memory hierarchy problems, confirm you can:

1. Registers to cache to RAM to storage pyramid
2. Write-through vs write-back cache policy
3. Virtual memory extends apparent RAM via paging

Revise the solved examples in Computer System Architecture — Morris Mano and one previous-year GATE or university paper for this unit.

Worked examples

Try the problem first — open the solution when you are ready to check.

AMAT estimation

Problem

Cache hit time 2 ns, miss rate 4%, miss penalty 80 ns. Find AMAT.

Solution

AMAT = 2 + 0.04×80 = 2 + 3.2 = 5.2 ns.

Conceptual check — Memory Hierarchy

Problem

In a Computer Architecture semester or GATE paper you are asked: "State the main assumption, the governing relation, and one practical consequence of memory hierarchy." What should a complete answer include?

📖 Standard books (India)

Computer System Architecture — Morris Mano
Read: Syllabus unit
CPU, memory hierarchy, and I/O

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