Memory and Programmable Logic

The number of addressable locations is 2 raised to the number of address lines; multiplying by the word width gives the total bit capacity. So a chip with 10 address lines and 8 data lines holds 2¹⁰ × 8 = 8192 bits (1 KB).

SRAM is fast and needs no refresh but uses six transistors per cell (low density); DRAM stores a bit on a capacitor (high density) but must be refreshed. ROM variants (mask, PROM, EPROM, EEPROM, flash) differ in how and how often they are programmed.

Relation 1 —

Write this relation with symbols exactly as in Digital Design — Morris Mano before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

Relation 2 —

Write this relation with symbols exactly as in Digital Design — Morris Mano before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

Relation 3 —

Write this relation with symbols exactly as in Digital Design — Morris Mano before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

Address decoding selects one chip (or bank) from a larger memory map; the higher address bits drive a decoder whose outputs are the chip-select lines, while the lower bits address within each chip.

Programmable logic implements combinational (and, in CPLD/FPGA, sequential) functions: a PLA has programmable AND and OR planes; a PAL fixes the OR plane; FPGAs use look-up tables and programmable interconnect for large designs.

Access time is how long after a valid address the data is available; cycle time is the minimum time between successive accesses — the two differ for DRAM because of precharge/refresh.

State assumptions explicitly before using any relation for memory and programmable logic — steady state, uniform properties, linear elastic material, ideal gas, incompressible flow, etc., as applicable.

Wrong assumptions invalidate the entire solution even when the formula is correct. In Digital Electronics viva and GATE descriptive questions, listing valid assumptions often earns separate marks.

1. Read the question and list given data with SI units (common in Digital Electronics papers).
2. Draw a neat labelled diagram where applicable — examiners in Indian universities award diagram marks even when arithmetic slips.
3. Identify which relation from this topic applies to memory and programmable logic.
4. Use equation 1: .
5. Use equation 2: .
6. Substitute values, compute, and verify units and sign (direction).
7. State conclusion in one line — e.g. safe/unsafe, stable/unstable, feasible/infeasible.

Memory and Programmable Logic appears in computers and embedded systems. In Indian electrical curricula this topic is tested because it connects theory to logic design and sequential circuits.

GATE and semester exams often combine memory and programmable logic with earlier units — revise prerequisites before attempting mixed problems.

Industry interview panels sometimes ask: "Where did you use memory and programmable logic?" — answer with a lab, mini-project, or plant visit example if possible.

• Computing capacity as address lines × data lines instead of 2^address × data
• Confusing bytes and bits in the total capacity
• Mixing up SRAM (no refresh) and DRAM (needs refresh)
• Forgetting the upper address bits drive chip-select decoding

Before attempting memory and programmable logic problems, confirm you can:

1. SRAM vs DRAM: speed vs density
2. ROM: mask, PROM, EPROM, EEPROM, flash
3. FPGA/CPLD for field-programmable logic implementation

Revise the solved examples in Digital Design — Morris Mano and one previous-year GATE or university paper for this unit.