Sequential Logic Design

Flip-flops store one bit and change state on the active clock edge (synchronous design). The D flip-flop simply latches its input (Q_{n+1} = D); the JK is universal (J = K = 1 toggles); the T toggles when T = 1.

Counters and shift registers are built by connecting flip-flops. A mod-N counter cycles through N states; the number of flip-flops needed is the smallest n with 2ⁿ ≥ N.

Relation 1 —

Write this relation with symbols exactly as in Digital Design — Morris Mano before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

Relation 2 —

Write this relation with symbols exactly as in Digital Design — Morris Mano before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

Relation 3 —

Write this relation with symbols exactly as in Digital Design — Morris Mano before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

State-machine design proceeds through a state diagram, state table, state assignment, excitation table (using the flip-flop characteristic equations) and finally the combinational next-state logic.

Setup time is how long data must be stable before the clock edge, and hold time how long after; violating them causes metastability, an unpredictable output. The maximum clock frequency is limited by t_clk-q + t_comb + t_setup along the critical path.

Mealy machines have outputs depending on state and input (can change between clocks); Moore machines have outputs depending on state only (change only at the clock edge), giving glitch-free outputs.

State assumptions explicitly before using any relation for sequential logic design — steady state, uniform properties, linear elastic material, ideal gas, incompressible flow, etc., as applicable.

Wrong assumptions invalidate the entire solution even when the formula is correct. In Digital Electronics viva and GATE descriptive questions, listing valid assumptions often earns separate marks.

1. Read the question and list given data with SI units (common in Digital Electronics papers).
2. Draw a neat labelled diagram where applicable — examiners in Indian universities award diagram marks even when arithmetic slips.
3. Identify which relation from this topic applies to sequential logic design.
4. Use equation 1: .
5. Use equation 2: .
6. Substitute values, compute, and verify units and sign (direction).
7. State conclusion in one line — e.g. safe/unsafe, stable/unstable, feasible/infeasible.

Sequential Logic Design appears in computers and embedded systems. In Indian electrical curricula this topic is tested because it connects theory to logic design and sequential circuits.

GATE and semester exams often combine sequential logic design with earlier units — revise prerequisites before attempting mixed problems.

Industry interview panels sometimes ask: "Where did you use sequential logic design?" — answer with a lab, mini-project, or plant visit example if possible.

• Using the wrong flip-flop characteristic equation in the excitation table
• Choosing too few flip-flops for the required number of states (need 2ⁿ ≥ N)
• Ignoring setup/hold timing when estimating maximum clock frequency
• Confusing Mealy and Moore output timing

Before attempting sequential logic design problems, confirm you can:

1. Synchronous: clock edge triggers state change
2. Setup and hold times prevent metastability
3. Counter, shift register, state machine design

Revise the solved examples in Digital Design — Morris Mano and one previous-year GATE or university paper for this unit.