Microprocessor Architecture

Microprocessor architecture defines internal units, buses, and instruction execution flow.

Key formulas & points

Skim these first — then read the full notes below.

  • BIU fetches while EU executes via prefetch queue
  • Flag register: ZF, CF, SF, OF, PF, AF
  • Real mode uses segmented addressing

Topic details

Introduction

Hamacher uses 8086-style concepts to explain datapath/control fundamentals. Indian B.Tech papers still include segmentation and BIU-EU pipelining as core historical architecture topics.

Key relations & formulas

Formulas (Indian textbook notation)

  • 8086:16bitdatabus,20bitaddressgives1MBspace8086: 16-bit data bus, 20-bit address gives 1 MB space

Formulas (Indian textbook notation)

  • registers:AX,BX,CX,DX+segment:offsetaddressingregisters: AX, BX, CX, DX + segment:offset addressing

Formulas (Indian textbook notation)

  • physical=segment×16+offsetphysical = segment \times 16 + offset

Notation and sign conventions

Relation 1 —
8086:16bitdatabus,20bitaddressgives1MBspace8086: 16-bit data bus, 20-bit address gives 1 MB space

Formulas (Indian textbook notation)

  • 8086:16bitdatabus,20bitaddressgives1MBspace8086: 16-bit data bus, 20-bit address gives 1 MB space
Write this relation with symbols exactly as in Microprocessor Architecture & Programming — Ramesh Gaonkar before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.
Relation 2 —
registers:AX,BX,CX,DX+segment:offsetaddressingregisters: AX, BX, CX, DX + segment:offset addressing

Formulas (Indian textbook notation)

  • registers:AX,BX,CX,DX+segment:offsetaddressingregisters: AX, BX, CX, DX + segment:offset addressing
Write this relation with symbols exactly as in Microprocessor Architecture & Programming — Ramesh Gaonkar before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.
Relation 3 —
physical=segment×16+offsetphysical = segment \times 16 + offset

Formulas (Indian textbook notation)

  • physical=segment×16+offsetphysical = segment \times 16 + offset
Write this relation with symbols exactly as in Microprocessor Architecture & Programming — Ramesh Gaonkar before substituting numbers. Examiners award partial marks for a correct setup even when arithmetic slips.

Concept in depth

The 8086 separates bus interface and execution functions to overlap fetch and execute. Segmentation extends addressability beyond 16-bit offset limits using segment registers. Control flags capture arithmetic and logic outcomes for conditional branching. Understanding this model helps decode timing and assembly behavior in peripheral interfacing problems.

Assumptions and validity limits

State assumptions explicitly before using any relation for microprocessor architecture — steady state, uniform properties, linear elastic material, ideal gas, incompressible flow, etc., as applicable.
Wrong assumptions invalidate the entire solution even when the formula is correct. In Microprocessors (Hardware) viva and GATE descriptive questions, listing valid assumptions often earns separate marks.

Step-by-step problem approach

1. Read the question and list given data with SI units (common in Microprocessors (Hardware) papers).
2. Draw a neat labelled diagram where applicable — examiners in Indian universities award diagram marks even when arithmetic slips.
3. Identify which relation from this topic applies to microprocessor architecture.
4. Use equation 1:
8086:16bitdatabus,20bitaddressgives1MBspace8086: 16-bit data bus, 20-bit address gives 1 MB space
.
5. Use equation 2:
registers:AX,BX,CX,DX+segment:offsetaddressingregisters: AX, BX, CX, DX + segment:offset addressing
.
6. Substitute values, compute, and verify units and sign (direction).
7. State conclusion in one line — e.g. safe/unsafe, stable/unstable, feasible/infeasible.

Applications & exam relevance

Microprocessor Architecture appears in embedded boards and kits. In Indian computer hardware curricula this topic is tested because it connects theory to MPU architecture and interfacing.
GATE and semester exams often combine microprocessor architecture with earlier units — revise prerequisites before attempting mixed problems.
Industry interview panels sometimes ask: "Where did you use microprocessor architecture?" — answer with a lab, mini-project, or plant visit example if possible.

Common mistakes in exams

Students frequently confuse logical and physical address and forget multiplication by 16 in segment calculation. Another common issue is wrong interpretation of carry versus overflow flags.

Quick revision checklist

Before attempting microprocessor architecture problems, confirm you can:
1. BIU fetches while EU executes via prefetch queue
2. Flag register: ZF, CF, SF, OF, PF, AF
3. Real mode uses segmented addressing
Revise the solved examples in Microprocessor Architecture & Programming — Ramesh Gaonkar and one previous-year GATE or university paper for this unit.

Worked examples

Try the problem first — open the solution when you are ready to check.

Physical address computation

Problem

Given CS = 2AF3H and IP = 1C20H, compute physical address.

Solution

Physical = CS×10H + IP = 2AF30H + 1C20H = 2CB50H.

Conceptual check — Microprocessor Architecture

Problem

In a Microprocessors (Hardware) semester or GATE paper you are asked: "State the main assumption, the governing relation, and one practical consequence of microprocessor architecture." What should a complete answer include?

📖 Standard books (India)

  • Microprocessor Architecture & ProgrammingRamesh Gaonkar

    Read: Syllabus unit

    8085/8086 — widely used in Indian colleges